Programmable delay circuits are well known in the art. These circuits have been extensively used in a variety of applications, mainly in the field of testing Very Large Scale Integrated circuits (VLSI). Typically, test systems have been known to require the generation of accurate timing signals for use as stimulus for a Device Under Test (DUT), oftentimes with delay increments ranging from a few picoseconds (ps) to several microseconds (us).
Various digital techniques have been proposed to generate relatively large delay steps, usually in the range of 2 and more nanoseconds (ns).
Y. E. Chang et al disclose a programmable timing generator capable of operating at frequencies of up to approximately 200 MHz in the IBM Technical Disclosure Bulletin, Vol. 20, No. 3, August 1977, p. 1027. This circuit has a cycle time which is continuously programmable from 5 to 2,500 ns with the time delay for a particular sequence of pulses being programmable from 0 to that cycle time.
Y. E. Chang et al further describe in U.S. Pat. No. 4,608,706 a high-speed programmable timing generator that uses a digital counter and comparator to generate delays in cycle time increments. Digital counters and comparators have typically been used by practitioners in the art to obtain variable timings for a variety of applications.
A second requirement of future test systems is the ability of changing "timing-on-the-fly", which is defined as allowing programmed delay values to change from one tester cycle to the next. With existing current minimum tester cycle times in the order of 2-4 ns, it is essential that a delay generator circuit be capable of responding to changes in the programmed value at this rate. Existing delay circuits cannot respond this fast, requiring clumsy arrangements of multiplexer circuits and the like, to select from a set of fixed delay generators.
This requirement can be met only by adding substantial number of circuits that include timing memories, counters and verniers that directly interface with a tester driver/load/comparator and which, in combination, generate programmable timing events with resolutions in the range of 10 ps. Such a circuit arrangement, described in the EDN issue of May 21, 1992, under the title of "ECL IC integrates 200 MHz ATE pin electronics", permits selecting a plurality of time sets "on-the-fly", thereby allowing timing to be changed cycle-by-cycle.
In another circuit arrangement described in the October 1990 issue of Electronic Product Design, an article entitled "High accuracy ASIC tester" by Dr. T. Tamama, pp. 39-42, shows a series of cascaded selectors (or demultiplexers) and corresponding parallel paths. Each delay path has a different value that requires extreme care during the design to ensure linearity.
Prior art circuits of this type suffer major drawbacks in their inability or at best, in their difficulty, of switching delay on-the-fly, particularly, in a high-frequency delay environment.